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A New Family of CMOS Cascode-Free Amplifiers with High Energy-Efficiency and Improved Gain


A New Family of CMOS Cascode-Free Amplifiers with High Energy-Efficiency and Improved Gain



von: Ricardo Filipe Sereno Póvoa, João Carlos da Palma Goes, Nuno Cavaco Gomes Horta

96,29 €

Verlag: Springer
Format: PDF
Veröffentl.: 10.08.2018
ISBN/EAN: 9783319952079
Sprache: englisch

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Beschreibungen

<p>This book addresses the need for energy-efficient amplifiers, providing gain enhancement strategies, suitable to run in parallel with lower supply voltages, by introducing a new family of single-stage cascode-free amplifiers, with proper design, optimization, fabrication and experimental evaluation. &nbsp;The authors describe several topologies, using the UMC 130 nm CMOS technology node with standard-VT devices, for proof-of-concept, achieving results far beyond what is achievable with a classic single-stage folded-cascode amplifier.&nbsp; Readers will learn about a new family of circuits with a broad range of applications, together with the familiarization with a state-of-the-art electronic design automation methodology used to explore the design space of the proposed circuit family.</p>
<p>Introduction.- Background and State-of-the-art.- Proposed Architectures and Practical Realizations.- Optimization Design and Simulation Results.- Integrated Prototypes and Experimental Evaluation.- Conclusions.</p>
<p>Ricardo F. S. Póvoa is a Post-Doctoral Researcher in the Integrated Circuits Group, within the Instituto de Telecomunicações, Lisboa, Portugal.<br><br>João C. da Palma Goes is a Professor at Faculdade de Ciências e Tecnologia, Universidade Nova de Lisboa, Lisboa, Portugal.<br><br>Nuno C. G. Horta is a Professor at Instituto Superior Técnico, Universidade de Lisboa, and a Senior Researcher in the Integrated Circuits Group, within the Instituto de Telecomunicações, Lisboa, Portugal.<br></p>
<div>This book addresses the need for energy-efficient amplifiers, providing gain enhancement strategies, suitable to run in parallel with lower supply voltages, by introducing a new family of single-stage cascode-free amplifiers, with proper design, optimization, fabrication and experimental evaluation.&nbsp; The authors describe several topologies, using the UMC 130 nm CMOS technology node with standard-VT devices, for proof-of-concept, achieving results far beyond what is achievable with a classic single-stage folded-cascode amplifier.&nbsp; Readers will learn about a new family of circuits with a broad range of applications, together with the familiarization with a state-of-the-art electronic design automation methodology used to explore the design space of the proposed circuit family.</div><div><br></div><div><ul><li>Introduces a new family of CMOS cascode-free amplifiers with high energy-efficiency and improved gain;<br></li><li>Describes innovative circuit topologies: the Voltage-Combiners biased OTA (supplied by a 3.3 V source); the Voltage-Combiners biased OTA with Current Starving, for higher gain and energy-efficiency (supplied by a 3.3 V source); the Folded Voltage-Combiners biased OTA (supplied by sources from 1.2 V to 0.9 V); and a Dynamic Voltage-Combiners biased OTA, for high performance analog-to-digital converters (supplied by a 1.2 V source);<br></li><li>Enables readers to reach better results than what is achievable with classic single-stage folded-cascode amplifiers, with state-of-the-art results in the context of dynamically biased amplifiers;<br></li></ul></div><p></p><p></p><div><br></div><div><br></div><div><br></div>
Introduces a new family of CMOS cascode-free amplifiers with high energy-efficiency and improved gain; Describes innovative circuit topologies: the Voltage-Combiners biased OTA (supplied by a 3.3 V source); the Voltage-Combiners biased OTA with Current Starving, for higher gain and energy-efficiency (supplied by a 3.3 V source); the Folded Voltage-Combiners biased OTA (supplied by sources from 1.2 V to 0.9 V); and a Dynamic Voltage-Combiners biased OTA, for high performance analog-to-digital converters (supplied by a 1.2 V source); Enables readers to reach better results than what is achievable with classic single-stage folded-cascode amplifiers, with state-of-the-art results in the context of dynamically biased amplifiers;

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