Cover
About the Authors
Preface
Acknowledgments
1 Introduction and Historical Perspective
1. 1.1 Introduction
2. 1.2 Discovery of X‐Rays, Radiation, and Subatomic Particles
3. 1.3 The Nuclear Age
4. 1.4 The Space Age
5. 1.5 Semiconductors – Revolution, Evolution, and Scaling
6. 1.6 Beginning of Ionizing Radiation Effects in Semiconductors
7. 1.7 Beginning of Single‐Event Effects in Semiconductors
8. 1.8 Summary and Closing Comments
9. References
2 Radiation Environments
1. 2.1 Introduction
2. 2.2 X‐Rays, Gamma Rays, and the Atom
3. 2.3 Natural Radioactivity
4. 2.4 The Space Environment
5. 2.5 The Nuclear Reactor Environment
6. 2.6 The Weapons Environment
7. 2.7 The Environment in High‐Energy Physics Facilities
8. 2.8 Summary and Closing Comments
9. References
3 Radiation Effects in Semiconductor Materials
1. 3.1 Introduction
2. 3.2 Basic Effects
3. 3.3 Charge Trapping in Silicon Dioxide
4. 3.4 Bulk Damage
5. 3.5 Summary and Closing Comments
6. References
4 Radiation‐Induced Single Events
1. 4.1 Introduction – Single‐Events Effects (SEE)
2. 4.2 Single‐Event Upset (SEU)
3. 4.3 SEU – Particle Sources
4. 4.4 Single‐Event Gate Rupture (SEGR)
5. 4.5 Single‐Event Transients (SETs)
6. 4.6 Single‐Event Latchup (SEL)
7. 4.7 Summary and Closing Comments
8. References
5 Radiation Testing
1. 5.1 Introduction
2. 5.2 Radiation Testing and Sources
3. 5.3 Summary and Closing Comments
4. References
6 Device Modeling and Simulation Techniques
1. 6.1 Introduction
2. 6.2 Device Modeling
3. 6.3 Radiation Effects on Semiconductor Devices
4. 6.4 Circuit Simulation
5. 6.5 Summary and Closing Comments
6. References
7 Radiation Semiconductor Process and Layout Solutions
1. 7.1 Introduction
2. 7.2 Substrate Hardened Technologies
3. 7.3 Oxide Hardening Technologies
4. 7.4 CMOS Latchup Process Solutions
5. 7.5 CMOS Substrates – High‐Resistance Substrates
6. 7.6 Wells
7. 7.7 Triple‐Well Technology
8. 7.8 Sub‐Collectors
9. 7.9 Heavily Doped Buried Layers (HDBL)
10. 7.10 Isolation Concepts
11. 7.11 Deep Trench
12. 7.12 Layout Solutions
13. 7.13 Summary and Closing Comments
14. References
8 Single‐Event Upset Circuit Solutions
1. 8.1 Introduction
2. 8.2 CMOS DRAM SEU Circuit Solutions
3. 8.3 CMOS SRAM SEU Circuit Solution
4. 8.4 Bipolar SRAM
5. 8.5 Bipolar SRAM Circuit Solutions
6. 8.6 SEU in CMOS Logic Circuitry
7. 8.7 Summary and Closing Comments
8. References
9 Latchup Circuit Solutions
1. 9.1 Introduction
2. 9.2 Power Supply Concepts
3. 9.3 Overshoot and Undershoot Clamp Networks
4. 9.4 Passive and Active Guard Rings
5. 9.5 Triple‐Well Noise and Latchup Suppression Structures
6. 9.6 System‐Level Latchup Issues
7. 9.7 Summary and Closing Comments
8. References
10 Emerging Effects and Future Technology
1. 10.1 Introduction
2. 10.2 Radiation Effects in Advanced Technologies
3. 10.3 Radiation Effects in Semiconductor Nanostructures
4. 10.4 Radiation Effects and Advanced Packaging
5. 10.5 Ruggedized Capability
6. 10.6 Radiation Models
7. 10.7 A Nuclear World
8. 10.8 Summary and Closing Comments
9. References
Index
End User License Agreement

List of Tables

Chapter 2
1. Table 2.1 K‐shell emission line energy for various X‐ray tube anode mat...
2. Table 2.2 Comparison of fitting parameters for the semiempirical mass f...
3. Table 2.3 Properties of naturally occurring and man‐made radionuclides.
4. Table 2.4 Comparison of the fission critical energy to the neutron bind...
5. Table 2.5 Representative radiation environments in a nuclear power plan...
Chapter 3
1. Table 3.1 Ion pair generation energy for various materials.
2. Table 3.2 Values ofZ, L _rad, and for calculating radiation length u...
3. Table 3.3 Radiation length and critical energy for integrated circuit a...
4. Table 3.4 Neutron energy classification.
5. Table 3.5 Expressions for neutron interactions with nuclei.
Chapter 5
1. Table 5.1 Representative US industry and government radiation effects s...
Chapter 6
1. Table 6.1 Model effort for the various types of radiation and effects.
2. Table 6.2 Device model development timeline.
3. Table 6.3 MOSFET compact model parameters for post‐radiation corners.
4. Table 6.4 BJT compact model parameters for post radiation corners.
5. Table 6.5 MOS safe operating area model parameters.
Chapter 7
1. Table 7.1 Bipolar parameters vs. p+/n+ space for CMOS PNPN structures w...
2. Table 7.2 Bipolar parameters for CMOS PNPN structures with combinations...
3. Table 7.3 Deep trench depth vs. guard ring metrics (F, and 1/F, and 1 −...
4. Table 7.4 Trench depth study and the “bipolar” and guard ring efficienc...
Chapter 10
1. Table 10.1 npn bipolar current gain comparison of planar vs FinFET.
2. Table 10.2 pnp bipolar current gain comparison of planar vs. FinFET.

List of Illustrations

Chapter 1
1. Figure 1.1 A Crookes cathode ray tube, showing the cathode, anode, and cro...
2. Figure 1.2 An X‐ray tube. Note the cathode (right) and the anode structure...
3. Figure 1.3 Geiger and Marsden apparatus (1913) designed to measure the ang...
4. Figure 1.4 Little Boy (left) and Fat Man (right) atomic bombs. Little Boy ...
5. Figure 1.5 Cut‐away view of the van Allen radiation belts, showing the inn...
6. Figure 1.6 The motion of trapped charged particles in the Earth's magnetos...
7. Figure 1.7 Example of a simulation code output: calculated constant intens...
8. Figure 1.8 The corresponding constant intensity flux contours for >400 MeV...
9. Figure 1.9 No clear idea yet of the real consequences: the Starfish Prime ...
10. Figure 1.10 Diagram of Earth orbits showing the location of a sample of sa...
11. Figure 1.11 Point contact transistor patent issued to J. Bardeen et al. in...
12. Figure 1.12 The “single‐poly” dielectrically isolated (DI) structure. Smal...
13. Figure 1.13 A log‐linear plot of Moore's law (or rule of thumb), showing t...
14. Figure 1.14 Normalized MOS device threshold and flatband voltage shifts at...
Chapter 2
1. Figure 2.1 Output from an X‐ray tube showing characteristic and bremsstrah...
2. Figure 2.2 X‐rays are produced by X‐ray florescence and bremsstrahlung. (a...
3. Figure 2.3 Binding energies for shell electrons.
4. Figure 2.4 Portion of the electromagnetic spectrum showing the energy rang...
5. Figure 2.5 X‐ray absorption diagram.
6. Figure 2.6 Comparison of the mass attenuation coefficients for lead and si...
7. Figure 2.7 Diagram of the Auger effect. (a) An incident electron e scatter...
8. Figure 2.8 Nuclear binding energy versus nucleon.
9. Figure 2.9 Nuclear binding energy showing the various energy components in...
10. Figure 2.10 Fermi gas model diagram, note that E _B is the binding energ...
11. Figure 2.11 Relative abundance of the chemical elements in Earth's upper c...
12. Figure 2.12 Half‐life of elements and their isotopes.
13. Figure 2.13 Superposition of the nuclear orbital angular energy in a finit...
14. Figure 2.14 Binding energies of nuclei comprised of an integer number of a...
15. Figure 2.15 Evolution of nuclear models in the years since the 1930s.
16. Figure 2.16 Illustration showing the effect that alpha and beta decay have...
17. Figure 2.17 The emitted alpha particle energy is dependent on the emission...
18. Figure 2.18 Feynman diagrams for β decay.
19. Figure 2.19 Typical energy spectrum for β− decay. Internal conversion elec...
20. Figure 2.20 Energy diagram for Cobalt‐60 β decay.
21. Figure 2.21 Portion of the nuclide chart showing decay mode.
22. Figure 2.22 The uranium series.
23. Figure 2.23 The thorium series.
24. Figure 2.24 The actinium series.
25. Figure 2.25 The neptunium series.
26. Figure 2.26 Daily sunspot area averaged over individual solar rotations....
27. Figure 2.27 Diagram of the Sun.
28. Figure 2.28 Diagram of the Sun's heliosphere and its interstellar interact...
29. Figure 2.29 Cross‐sectional view of the van Allen radiation belts showing ...
30. Figure 2.30 Structure of the Earth's magnetosphere under the influence of ...
31. Figure 2.31 Galactic cosmic ray energy spectrum. Fluxes of nuclei of the p...
32. Figure 2.32 Galactic cosmic ray flux as a function of atomic mass, showing...
33. Figure 2.33 Diagram of a cosmic ray cascade.
34. Figure 2.34 The atmospheric 1–10 MeV equivalent neutron flux as a function...
35. Figure 2.35 Fission reaction showing timescale and decay of the fission fr...
36. Figure 2.36 Dependence of the prompt fission neutron spectrum on the kinet...
37. Figure 2.37 The Crossroads Baker nuclear event at Bikini Atoll. This was a...
38. Figure 2.38 Calculated time dependence of the gamma ray energy output per ...
Chapter 3
1. Figure 3.1 Bragg curve for 5.49 MeV alpha particles in air.
2. Figure 3.2 Particle interaction with a single electron.
3. Figure 3.3 Mean excitation energy (relative) versus atomic number.
4. Figure 3.4 Stopping power calculation diagram.
5. Figure 3.5 Nuclear and electronic stopping power for protons in silicon....
6. Figure 3.6 Bremsstrahlung (braking radiation) for an electron.
7. Figure 3.7 Diagram for Larmor formula derivation.
8. Figure 3.8 Diagram for Larmor formula derivation (detail).
9. Figure 3.9 Representation of the dipole radiation field from a particle un...
10. Figure 3.10 Two tree‐level Feynman diagrams for the scattering between two...
11. Figure 3.11 Fractional energy loss per radiation length in lead as a funct...
12. Figure 3.12 Total neutron cross section versus neutron energy for ²⁸Si....
13. Figure 3.13 Laboratory (L) and Center of Mass (C) reference frames.
14. Figure 3.14 Photoelectric effect.
15. Figure 3.15 Compton scattering.
16. Figure 3.16 Pair production.
17. Figure 3.17 Basic mechanism for trapped positive charge in SiO₂: (a) Cross...
18. Figure 3.18 (a) Representation of the Coulomb field between an electron an...
19. Figure 3.19 Fractional yield as a function of applied electric field for 1...
20. Figure 3.20 Time evolution of a section of an ionization track under the i...
21. Figure 3.21 Fractional yield versus applied field for columnar recombinati...
22. Figure 3.22 Region of application for columnar and geminate recombination ...
23. Figure 3.23 Dependence of fractional yield in SiO₂ on ion LET with electri...
24. Figure 3.24 Band diagram showing the transport of generated charge in a MO...
25. Figure 3.25 Fragment of the SiO₂ structure.
26. Figure 3.26 Defects in SiO₂: (a) Example of correct bonding; (b) oxygen va...
27. Figure 3.27 E′ centers: (a) oxygen vacancy O ≡ Si−Si ≡ O; (b) traps a hol...
28. Figure 3.28 Normalized midgap voltage shift recovery curves shifted to coi...
29. Figure 3.29 Comparison of (a) discrete‐time random‐walk; and (b) continuou...
30. Figure 3.30 Illustration of hole transport via polaron hopping between two...
31. Figure 3.31 Structural model of the (100) Si−SiO₂ interface.
32. Figure 3.32 Update to the Deal convention suggested by Fleetwood.
33. Figure 3.33 A model for hole trapping at interfacial E' centers based ...
34. Figure 3.34 Time‐dependent threshold voltage recovery of n‐channel MOSFET....
35. Figure 3.35 Bias dependency of the interface state buildup after irradiati...
36. Figure 3.36 Crystal damage caused by neutron irradiation.
37. Figure 3.37 Resistivity for uniformly doped n‐type and p‐type silicon vers...
Chapter 4
1. Figure 4.1 Nondestructive single‐event effects.
2. Figure 4.2 Destructive single‐event effects.
3. Figure 4.3 Single‐event upset.
4. Figure 4.4 Multiple‐bit upset (MBU).
5. Figure 4.5 Single‐event transient.
6. Figure 4.6 Single‐event snapback (SESB).
7. Figure 4.7 Single‐event latchup.
8. Figure 4.8 Single‐event gate rupture (SEGR).
9. Figure 4.9 Single‐event upsets in technology types.
10. Figure 4.10 Single‐event upsets particle source.
11. Figure 4.11 Uranium series.
12. Figure 4.12 Thorium series.
13. Figure 4.13 Electron hole pair charge transfer from alpha particle events....
14. Figure 4.14 Circuit schematic highlighting the charge transfer processes w...
15. Figure 4.15 Pion capture.
16. Figure 4.16 Neutrons.
17. Figure 4.17 Protons.
18. Figure 4.18 Heavy ions.
19. Figure 4.19 Single‐event gate rupture (SEGR).
20. Figure 4.20 Power transistor SEGR.
21. Figure 4.21 VMOS SEGR.
22. Figure 4.22 FinFET SEGR.
23. Figure 4.23 Single‐event latchup (SEL).
24. Figure 4.24 Cross section highlighting minority carrier transport.
25. Figure 4.25 Semiconductor device simulation time sequence of an alpha part...
26. Figure 4.26 Semiconductor device simulation of the electric potentials as ...
Chapter 5
1. Figure 5.1 Net positive charge yield in silicon dioxide for 10 keV X‐rays,...
2. Figure 5.2 A classic set of curves: Where is the bottom? Input offset volt...
3. Figure 5.3 A Gammacell 220^{TM 60}Co gamma ray irradiator built by Atomic Ene...
4. Figure 5.4 Preproduction drawings of the Hopewell Designs, Inc. Model GR42...
5. Figure 5.5 The fixturing section of a modified Hopewell Designs N40 vault‐...
6. Figure 5.6 Charge collection in a CMOS semiconductor device structure, sho...
7. Figure 5.7 Shielding does you no good at all: Fe cosmic ray energy spectra...
8. Figure 5.8 The K500 Cyclotron installation at Texas A&M. A 50 kilogauss su...
9. Figure 5.9 An in‐air test station located at the end of a TAMU beam line. ...
10. Figure 5.10 Block diagram showing the components in a typical TPA laser si...
11. Figure 5.11 14 MeV neutron generator for displacement damage and single ev...
12. Figure 5.12 Trapped proton fluence as a function of proton energy in a 705...
13. Figure 5.13 Exploded view of a typical flash X‐ray system. The charging vo...
14. Figure 5.14 Pulserad 112A Flash X‐ray system used for prompt dose testing ...
Chapter 6
1. Figure 6.1 Netlist comparison between single component (left) and composit...
2. Figure 6.2 Cross section of four integrated MOS capacitors (not to scale)....
3. Figure 6.3 C‐V plot for the n‐type varactor.
4. Figure 6.4 Post‐radiation high‐frequency C‐V plot for the n‐type varactor....
5. Figure 6.5 Pre‐ and post‐radiation I_ds versus V_gs log‐linear plots for NMO...
6. Figure 6.6 NMOS layout view and cutline cross sectional views for STI and ...
7. Figure 6.7 Separation of channel and sidewall devices in the MOS model.
8. Figure 6.8 Cross section of three generations of bipolar transistor.
9. Figure 6.9 The gated lateral PNP (GLPNP) device.
10. Figure 6.10 Gummel and beta versus Ic plots for an NPN transistor showing ...
11. Figure 6.11 Comparison of 15V planar and polysilicon emitter NPN transisto...
12. Figure 6.12 Macromodel for a quasi‐vertical NDMOS device.
13. Figure 6.13 Cross section of the NJET device.
14. Figure 6.14 Process design kit (PDK) file organization.
15. Figure 6.15 Corner and model file examples.
16. Figure 6.16 Implementation of post‐rad corner and section files.
17. Figure 6.17 Cross section of an NPN transistor showing possible single‐eve...
18. Figure 6.18 Single‐event current pulse circuit.
Chapter 7
1. Figure 7.1 Substrate hardened technologies.
2. Figure 7.2 (a) SIMOX SOI cross section illustrating a SOI MOSFET. (b) SIBO...
3. Figure 7.3 Silicon on sapphire (SOS) structure.
4. Figure 7.4 Silicon on nothing (SON) structure.
5. Figure 7.5 Latchup trigger voltage as a function of substrate resistance....
6. Figure 7.6 Parasitic NPN and PNP bipolar current gain product as a functio...
7. Figure 7.7 Latchup I‐V simulation versus p+/n+ spacing.
8. Figure 7.8 Bipolar PNP current gain vs retrograde n‐well structure.
9. Figure 7.9 Holding voltage versus pulse width for different retrograde wel...
10. Figure 7.10 Dual well technology cross section.
11. Figure 7.11 Cross section of the vertical bipolar in a scaled p‐well and p...
12. Figure 7.12 P‐well and p+ connecting implant.
13. Figure 7.13 Fully separated triple‐well technology.
14. Figure 7.14 Merged triple‐well technology.
15. Figure 7.15 PNP bipolar gain – merged triple well vs. dual well.
16. Figure 7.16 NPN bipolar gain – merged triple well vs. dual well.
17. Figure 7.17 Cross section of the BILLI structure.
18. Figure 7.18 Heavily doped buried layer (HDBL) – vertical doping profile un...
19. Figure 7.19 Heavily doped buried layer (HDBL) – vertical doping profile un...
20. Figure 7.20 Minority carrier lifetime versus heavily doped buried layer (H...
21. Figure 7.21 (a) Latchup with and without HDBL; (b) Latchup simulation vers...
22. Figure 7.22 Buried guard ring (BGR) cross section.
23. Figure 7.23 Latchup simulation with buried guard ring (BGR).
24. Figure 7.24 (a) Holding voltage versus shallow trench isolation (STI) dept...
25. Figure 7.25 (a) Trench isolation (TI); (b) CMOS PNPN latchup structure wit...
26. Figure 7.26 Deep trench (DT) PNPN latchup structure cross section.
27. Figure 7.27 CMOS latchup trigger voltage, V_TR, results of the deep trench ...
28. Figure 7.28 (a) Latchup structure with deep trench and sub‐collector; (b) ...
29. Figure 7.29 (a) MOSFET active region with parasitic isolation device (PID)...
Chapter 8
1. Figure 8.1 Types of circuits sensitive to single‐event upsets (SEU).
2. Figure 8.2 CMOS DRAM features that influence SEU.
3. Figure 8.3 CMOS DRAM substrate plate trench (SPT) capacitor cell.
4. Figure 8.4 CMOS DRAM – 16 Mb DRAM trench cell.
5. Figure 8.5 CMOS DRAM with SRAM array – 16 Mb DRAM.
6. Figure 8.6 CMOS SRAM SEU circuit solution.
7. Figure 8.7 CMOS 4‐D SRAM cell.
8. Figure 8.8 CMOS SRAM 6‐D cell circuit topology.
9. Figure 8.9 CMOS 6‐D SRAM cell with cross‐coupling resistor elements.
10. Figure 8.10 CMOS 13‐D SRAM cell.
11. Figure 8.11 Bipolar SRAM cell types.
12. Figure 8.12 Bipolar SRAM cell with resistor loads.
13. Figure 8.13 Bipolar SRAM cell with dual emitter, resistor load, and Schott...
14. Figure 8.14 Bipolar SRAM cell with PNP load.
Chapter 9
1. Figure 9.1 Power supply current‐limiting resistor element.
2. Figure 9.2 Power supply current‐limiting current source.
3. Figure 9.3 Power supply current‐limiting voltage regulator.
4. Figure 9.4 CMOS latchup power supply decoupling network.
5. Figure 9.5 Power supply decoupling network utilizing active clamp networks...
6. Figure 9.6 Passive clamp network.
7. Figure 9.7 CMOS active clamp network.
8. Figure 9.8 I‐V characteristics of an active clamp network.
9. Figure 9.9 Reflection coefficient of an active clamp network.
10. Figure 9.10 Dynamic threshold triple well body‐ and gate‐coupled ESD netwo...
11. Figure 9.11 Dynamic threshold triple well active clamp network.
12. Figure 9.12 Active guard ring with n‐well junction electrically connected ...
13. Figure 9.13 Active guard ring with n‐well junction electrically connected ...
14. Figure 9.14 Active guard ring with n‐well, and a n+ buried layer, and a pa...
15. Figure 9.15 Active guard ring noise and latchup suppression network.
16. Figure 9.16 Active guard ring noise and latchup suppression network with R...
17. Figure 9.17 Compensation based active guard ring with analog multiplier‐di...
Chapter 10
1. Figure 10.1 Bulk CMOS FinFET structure.
2. Figure 10.2 2.5‐D multi‐chip assembly.
3. Figure 10.3 3‐D multi‐chip structure.

About the Authors

Stephen J. Gaul received his B.S. and M.S. in Electrical Engineering Science from Iowa State University in 1980 and 1982, respectively. His undergraduate study focused on fields and waves, analog circuit design, and physics. His research during graduate study was supported by a grant from 3M (Minneapolis, Minnesota).

In 1983 Gaul joined Harris Semiconductor in Palm Bay, Florida. Harris Semiconductor was part of Harris Corporation, with many divisions, and Steve worked sequentially through several. These included the CMOS division as a process engineer, Bipolar division developing device simulation models, and the Custom Integrated Circuit Division working as a device engineer on a variety of programs to develop radiation hardened and other analog solutions. Several of these programs included process as well as circuit developments.

In the late 1980s, Gaul was doing research on bonded‐wafer silicon on insulator (SOI) as a replacement for dielectric isolation (DI) wafer material processing. He fabricated the first bonded wafer bipolar devices at Harris Semiconductor in 1989 and also developed bonded‐wafer material process flows and trench isolation for the first such analog components fabricated at Harris Semiconductor in the early 1990s. By the mid 1990s, Gaul had worked on a number of projects, including improving defect density in bonded/trenched material processing and solving an electro‐chemical mismatch issue on circuits using thin film resistors. Additionally, he worked on yield enhancement and migration of DI telecom circuits to bonded wafer substrates.

Gaul joined Unitrode in Merrimack, NH, in 1995 to develop a bonded‐wafer trench isolation process as a cost improvement for existing bulk isolated processes. He improved the yield of this process from 0% to greater than 90% in less than six months. Gaul also investigated safe operating area (SOA) issues in output devices in a 20 V BiCMOS process fabricated at an external foundry.

In 1997 Gaul returned to Harris Semiconductor, working on yield and process enhancement on submicron BCDMOS processes. He completed in‐house college‐level classes in RF circuit design and DSP in 1998, and his work at this time increasingly brought him into contact with circuit design tools and systems. By 1999, Gaul had taken a position as a process design kit (PDK) developer with Harris's design automation team.

Harris Semiconductor became a standalone company in late 1999 called Intersil (based on the Santa‐Clara company that was part of the 1988 Harris Semiconductor acquisition of GE Solid State), and Gaul turned to managing PDK and Design Systems for all circuit design teams at Intersil. He pioneered the use and repurposing of design system code for devices (pcells) providing rapid development of PDKs to keep pace with the corresponding rapid development of newer submicron processes. His process and device background was leveraged to improve electrostatic discharge (ESD) performance in existing processes and to cost‐improve an in‐house 0.6‐μm semiconductor process using a software shrink of 10%; this shrink was instrumental in bridging the design community to a smaller geometry BCDMOS that was in development, with a large cost saving to Intersil.

Gaul currently manages the engineering design infrastructure at Renesas Electronics Americas Inc. (REA), which purchased Intersil in 2017. His interests include radiation effects, circuit hardening, IP security, export law, and small‐town government. Gaul has written and presented 17 papers at refereed conferences, including the SOI Technology Conference, RHET, IEEE Nuclear and Space Radiation Effects Conference (NSREC), and the Journal of Radiation Effects Research and Engineering. He holds 40 US issued patents in a variety of areas, from semiconductor process flows, device design, ESD devices, radiation hardened devices, methods of forming SOI materials, improvements in trench isolation, 3D circuits, silicon on diamond (SOD), engineering design automation (EDA) software, and circuit solutions.

Nicolaas van Vonno has a strong background in the design, development, and production of high‐performance semiconductor integrated circuits, predominantly for radiation‐hardened space and defense applications. Specific areas of expertise include analog and mixed‐signal technology, radiation effects and semiconductor device radiation hardening.

Van Vonno received his Bachelor of Science degree in electrical engineering from the University of Florida in 1966. He then joined Harris Semiconductor (then Radiation, Incorporated, which was subsequently acquired by Harris Corporation) as a reliability engineer, with an initial assignment in reliability assurance for the US Navy Polaris and Poseidon SLBM programs, gaining experience in radiation effects, hardening technology, packaging, device fabrication, and quality assurance. Later, he transferred to a device engineering group, where he was responsible for device design, process development, and design/layout support. During this assignment, he participated in a broad range of projects reflecting Harris's support of many diverse technologies, including early metal‐gate CMOS and silicon‐on‐sapphire (SOS) processes. As a device engineering supervisor, he led a group of device designers, with representative projects including MOS hardness issues and radiation testing in the total ionizing dose, neutron and transient gamma environments.

In 1982, Van Vonno was promoted to director, Analog Product Development, with responsibilities in the design, development, and transfer to production of analog circuits for tactical, strategic, and space applications. Projects included the development of a broad range of analog parts for the Trident II SLBM program and development of a series of hardened analog signal processing circuits for the MX (Peacekeeper) program, as well as the development of mixed‐signal chip sets for tactical applications and the development of mixed‐signal design and verification methodologies, with Cadence as a technical partner. Other projects included the development of a radiation‐hardened cryogenic analog CMOS process for hardened 77 K and 40 K applications and the design of hardened readout multiplexer chips for use in directly hybridized HgCdTe IR focal plane array imagers.

Van Vonno was promoted to senior scientist in 1994, with responsibilities in radiation effects in electronics, technology development, and advanced projects. He then led the development of an innovative integrated fingerprint sensor using RF field technology. This project culminated in the successful spinoff of Authentec, Incorporated from Harris Semiconductor, and the eventual sale of Authentec, Inc. to Apple. The RF fingerprint sensor is currently a key feature of the Apple iPhone.

Van Vonno is currently a principal engineer with Intersil, a Renesas Company, Palm Bay, Florida. In this capacity, he is responsible for customer support and radiation effects research for the space product line, with added assignments in product development, legal support, and export control issues. He is an active researcher in enhanced low‐dose rate ionizing radiation sensitivity (ELDRS) phenomena in complementary bipolar processes. He has been an active participant in the JEDEC community, including the JEDEC JC13.4 Radiation Effects Assurance committee. He is an active participant in business development and customer support activities in Europe and is fluent in several languages.

Currently, Van Vonno holds 16 US patents in the areas of silicon device processing, optics, packaging, and biometric sensing. He has over 60 refereed publications and conference presentations and is a Life Senior Member of IEEE. He has participated in a wide range of professional activities, including IEEE and international conference assignments. He has been an active participant in the IEEE Nuclear and Space Radiation Effects Conference (NSREC), with assignments including poster session chairman, guest editor, session chairman, awards committee chairman, short course instructor, and short course chairman. Other IEEE activities include two three‐year terms as a member at large of the IEEE Radiation Effects Steering Group (RESG) and three years as vice‐chairman, publications, of RESG. He served as chairman of the 2001 IEEE Radiation Effects Data Workshop and was chairman of the local arrangements of the 2006 Nuclear and Space Radiation Effects Conference. Van Vonno received the IEEE Radiation Effects Award in 2009.

Dr. Steven H. Voldman received his BS in Engineering Science from the University of Buffalo (1979); a first M.S. electrical engineering (EE) (1981) from Massachusetts Institute of Technology (MIT); a second M.S. EE degree from MIT; an MS in Engineering Physics (1986), and a PhD in EE (1991) from the University of Vermont under IBM's resident study fellow program.

In 1977 and 1978, Dr. Voldman interned at the Robert E. Ginna nuclear plant as support for the nuclear engineer. He was a member of the MIT Magnetic Mirror Fusion experimental research group with a specialization in plasma physics from 1979 to 1981. In 1982, he was the first person in the IBM corporation to address alpha particle effects in bipolar static ram (SRAM) applications. Dr. Voldman worked with G. Sai‐Halasz on the development of the first SER alpha particle Monte Carlo simulation for the bipolar SRAM products. In 1984, he was assigned to IBM laboratory staff to develop a six‐device cell CMOS SRAM SER Monte Carlo alpha particle simulation. In 1985, he was a member of the proton and neutron cosmic ray testing effort of DRAM and SRAM IBM products to evaluate the effect of cosmic rays on terrestrial applications. In 1984, Dr. Voldman also worked on CMOS latchup for the IBM technologies. He has been involved in latchup technology development for 30 years. He worked on both technology and product development in Bipolar SRAM, CMOS DRAM, CMOS logic, SOI, BiCMOS, Silicon Germanium (SiGe), RF CMOS, RF SOI, smart power, and image processing technologies.

In 2008, Dr. Voldman was a member of the Qimonda DRAM development team, working on 70, 58, and 48 nm CMOS technology. That year, he also initiated a limited liability corporation (LLC), and worked at headquarters in Hsinchu, Taiwan, for Taiwan Semiconductor Manufacturing Corporation (TSMC) as part of the 45 nm ESD and latchup development team. From 2009 to 2011, he was a senior principal engineer working for the Intersil Corporation on ESD and latchup development working on analog and power applications. His work at Intersil involved semiconductor development of analog and digital mixed signals, SiGe, bipolar‐CMOS‐DMOS (BCD) power, and power SOI technologies. In 2013, Dr. Voldman was a member of the Samsung Electronics development team working on latchup development in 14 nm technology.

Dr. Voldman is the first IEEE Fellow in the field of ESD for “Contributions in ESD protection in CMOS, Silicon On Insulator and Silicon Germanium Technology.” He was chairman of the SEMATECH ESD Working Group, from 1995 to 2000. In his SEMATECH Working Group, the effort focused on ESD technology benchmarking, the first transmission line pulse (TLP) standard development team, strategic planning, and JEDEC‐ESD Association standards harmonization of the human body model (HBM) standard. From 2000 to 2010, as chairman of the ESD Association Work Group on TLP and very‐fast TLP (VF‐TLP), his team was responsible for initiating the first standard practice and standards for TLP and VF‐TLP. He has been a member of the ESD Association board of directors and education committee. He initiated the “ESD on Campus” program, which was established to bring ESD lectures and interaction to university faculty and students internationally. The ESD on Campus program has reached over 40 universities in the United States, Singapore, Taiwan, Malaysia, The Philippines, Thailand, India, China, and Africa.

Dr. Voldman has taught short courses and tutorials on ESD, latchup, and invention in the United States, China, Singapore, Malaysia, and Israel. He holds more than 260 US patents, in the area of ESD and CMOS latchup. He has served as an expert witness in patent litigation cases associated with ESD and latchup.

Dr. Voldman has also written articles for Scientific American and is an author of a 10‐book series on ESD, electrical overstress (EOS), and latchup, including: ESD: Physics and Devices, ESD: Circuits and Devices, ESD: Radio Frequency (RF) Technology and Circuits, ESD: Failure Mechanisms and Models, and ESD: Design and Synthesis, Latchup, EOS, ESD: Analog Design and Synthesis, ESD Basics: From Semiconductor Manufacturing to Product Use, and ESD Testing: Components and Systems, as well as contributing to the book Silicon Germanium: Technology, Modeling and Design, and international Chinese editions of the ESD books. He is also a chapter contributor to the text Nanoelectronics: Nanowires, Molecular Electronics, and Nano‐Devices.

Wesley H. Morris received his BS in Physics and Chemistry (dual majors) from Florida State University in 1977.

In 1981, Morris began his career at RCA Solid State as a semiconductor device engineer and worked there until 1986. His first job involved transferring a special Rad Hard manufacturing process developed at RCA Princeton labs from the Somerville Technology center to RCA's wafer manufacturing lab in Florida to begin manufacturing Rad Hard standard chip products. Morris successfully integrated and implemented the Rad Hard process and production line in Florida to begin manufacturing RHSOS products using silicon on sapphire (SOS) wafers. RCA began designing and producing SOS Rad Hard SRAMS, microprocessors (1802, 1804) and ASICs using the Rad Hard SOS wafer manufacturing process. Several RH SOS devices were selected and flown on JPL's Galileo and Jupiter missions and other NASA/DOD satellite systems, including the GPS satellite (MilStar) and first DBS (Direct TV) satellites included with RH SOS components in the satellite electronic payloads. In 1986, RCA awarded Morris the RCA solid‐state division award for technology excellence for his development work with the RH SOS project. The RH SOS development team were also nominated for RCA's Sarnoff award.

In 1986, Mr. Morris joined Harris Semiconductor as a principal engineer in Palm Bay, Florida, and was assigned to the military and aviation (MAD) division supporting the development of (novel) SOI wafers to develop a radiation hard manufacturing process using the silicon on insulator (SOI) wafer. At the time, RH CMOS SOI products were produced using SIMOX SOI technology that use ion implantation to form the buried oxide layer.

In 1988, after successfully developing and demonstrating fully functional 0.7 μm RH SOI SRAM memories, he moved to Austin, Texas, to represent the company at SEMATECH, which was a USA semiconductor industry research consortium formed by the top 10 US semiconductor companies to focus on improving silicon manufacturing tooling. His first assignment was to transfer IBM's 4Mb DRAM back end of line (BEOL) process from IBM to SEMATECH in Austin. After that, he was put in charge of TCAD modeling for SEMATECH process developments supporting phase 2 and 3 manufacturing processes, as well as working with SEMATECH'S wafer Fab and the electrical device test lab to set up integration and tool selections SEMEATECH would use for all the manufacturing and device test operations.

In 1992, Morris proposed and initiated the Vertically Modulated Well project, which was to develop a new approach to wafer doping and wafer manufacturing architecture to simplify the CMOS manufacturing process and reduce cycle time, wafer manufacturing costs, and advance CMOS device isolation scaling. The problem was, legacy methods used for bulk silicon isolation needed to prevent latchup as CMOS scaling evolved to increase latchup resistance. Wafer production costs were also barriers. In 1995, the VMW project was successfully integrated into two SEMATECH member companies, AMD and NCR (Lucent), and robust latchup mitigation method and lower wafer costs were proven out. It was a good start at the right time.

In 1993, Morris founded Silicon Engineering Inc., which provided CMOS engineering (consulting) services to both SEMATECH and the SEMI industry for TCAD modeling, process, and chip developments. He began working with Eaton Corporation in Beverly, Massachusetts, in 1995, supporting EATON's global launch of the high‐energy implant tools and the HDBL concept, which was developed at SEMATECH. He provided a technical interface to Eaton's customers and promoted adoption of the high‐energy implant technology and sales (EATON/Axcelis) of implant tools at foundries in SE Asia (Taiwan, South Korea, Singapore), and, the United States and Europe.

In 2003, Morris was invited to publish new work at the IRPS conference and presented data for the first time that by implementing a novel boron doping structure called the buried guard ring; any bulk silicon CMOS device could be made latchup immune. Up to this time, this was considered impossible for bulk wafers and only possible with SOS or SOI thin‐film technology. BGR was a better structure than the HDBL.

In 2004, Morris founded Silicon Space Technology, serving as CEO, CTO, and inventor of the company's RH/HT process and device IP. During this time, he led the company developments of a RH/HT technology platform based on modifications to the manufacturing process and IC design architecture to manufacture RH/HT standard products using commercial foundries. The technology developed enabled hardening of advanced (bulk) CMOS devices for operation in both radiation and high‐temperature environments. Highlights of the work were published at the HiTEN conferences in 2011, 2014, and 2015. SST proved that bulk CMOS devices could be hardened and manufactured in commercial foundries to operate reliably in both high‐radiation and high‐temperature environments.

In 2014, SST provided multiple RH/HT IC components and also a company test board design to develop an experimental flight controller (board) co‐developed with COSMAIC for the RHEME project. Using only RH/HT devices (SRAMS and Microcontrollers, and ASIC), the flight boards would be launched in three different Earth orbits aboard USAF/NASA experimental satellites. RHEME 1 was launched in March 2017 and mounted outside the International Space Station directly in the space environment. By June 2019, RHEME 1 had completed 806 days in space without any component or system failures. A paper summarizing results for the RHEME 1 flight was published at the 2018 NSREC conference. RHEME 2 was launched in December 2018 aboard an AF Satellite into an MEO/Polar orbit, again mounted outside the satellite (directly in space). RHEME 3 is scheduled for launch in December 2019. His work at SST proved that bulk silicon wafers could be designed and manufactured at modern wafer fabs (IDM or foundry) using IP he invented to modify the processes to withstand extremely high levels of radiation and high temperatures > 250C, and findings were published at IMAP'S HiTEN conferences in 2011, 2014, and 2015.

In 2017, Wes Morris founded Silicon‐X Corporation and is currently active as technology consultant.

Preface

The world has certainly changed since the first satellite was launched into orbit (Sputnik, October 4, 1957). Now, many nations as well as commercial companies have launch capabilities, and there is an ever‐increasing number of objects in Earth's orbit. The Union of Concerned Scientists (UCS) Satellite Database provides a good estimate of the current satellite count based on open‐source information, indicating over 1900 operational satellites currently in orbit around the Earth (1957 as of November 30, 2018). While there are satellites that serve military purposes, the majority serve commercial purposes – purposes like GPS, communications, and weather monitoring. All of these orbiting objects rely on radiation‐hardened electronics in order to stay operational in the space environment.

Designing for the space environment or any number of other radiation environments requires skills and knowledge that design engineers are not likely to encounter or learn while designing for terrestrial purposes. Integrated Circuit Design for Radiation Environments fills the knowledge gap, providing a front‐to‐back guide for designing integrated circuits intended for radiation environments. The text is divided roughly into three sections. The first of these includes Chapters 1 through 4 and provides the fundamental background history, the sources of radiation, essential nuclear physics, and basic semiconductor effects knowledge. Chapters 5 and 6 are aimed at two of the practical aspects of designing for radiation environments, radiation testing, and the development of device models. The remaining chapters are devoted to radiation‐hardening topics such as semiconductor processing and layout, SEU reduction, latchup prevention, and a look at some advanced topics.

Chapters 1 through 4 of Integrated Circuit Design for Radiation Environments cover the historical aspects of radiation as well as the fundamentals needed by the practitioner. Chapter 1 provides the reader with a narrative of the role of radiation, since its discovery highlighting its impact on the evolution of integrated circuits and their use in radiation environments. The various radiation environments are presented in Chapter 2, starting with an overview of the relevant atomic and nuclear physics. The aim of this chapter is fulfilled as the various radiation environments are then discussed in turn. Chapters 3 and 4 cover the cumulative and transient effects of radiation, respectively, on semiconductor materials and structures. These are two very important chapters, as they cover essential fundamentals for anyone designing or evaluating radiation‐hardened integrated circuits. Chapter 3 introduces the idea that radiation loses energy as it traverses the solid state. The various energy loss mechanisms for charged particles, electrons, neutrons, and photons traversing matter are discussed in the first half of the chapter. The remaining half of Chapter 3 discusses charge trapping and transport in silicon dioxide, including bulk and interfacial effects, two very important concepts for understanding the effects of total ionizing dose (TID) in integrated circuits. Transient effects caused by cosmic rays and other sources of radiation are a major concern in the space environment, and these are presented and discussed in Chapter 4. There are many types of transient effects besides the ambiguous yet ubiquitous single‐event upset (SEU) description, including multiple‐bit upset (MBU), single‐event transient (SET), single‐event functional interrupts (SEFIs), single event disturb (SED), single‐event snapback (SESB), single‐event latchup (SEL), single‐event burnout (SEB), single‐event gate rupture (SEGR), and single‐event hard error (SHE). All of these are discussed in Chapter 4.

Simulation is the main subject discussed in Chapters 5 and 6, although from two completely different aspects. The ability to simulate radiation environments for testing and qualification purposes is covered in Chapter 5. The types of simulated environment needed for testing depends on the actual radiation environment, but can include TID, single‐event effects (SEEs), neutron or proton irradiation, and transient gamma testing. The simulated radiation environments as well as the equipment and facilities available for testing are discussed. A review of circuit simulators, device models, and post‐radiation device characteristics is provided in Chapter 6. The radiation effects on various devices are discussed after an introductory section covering circuit simulators, intrinsic models, and device modeling.

Chapters 7 through 9 take a closer look at radiation hardening from the viewpoints of semiconductor process and layout techniques, SEU reduction, and latchup suppression. Chapter 10 discusses radiation effects in advanced technologies. A good review of semiconductor process and layout‐hardening methods is provided in Chapter 7Chapter 8Chapter 9Chapter 10

The study of radiation effects and radiation effects hardening in electronic circuits is indeed a deep dive, considering the efforts of the many researchers who have contributed to the current state of the art. Integrated Circuit Design for Radiation Environments is intended to be a starting point for study aimed at novice as well as experienced circuit designers. While it is impossible to cover all of the prior research in one text, the authors hope that this text provides the essential knowledge about radiation environments, effects, and hardening needed by the circuit design community.

Enjoy the text,

Stephen J. Gaul

Nicolaas van Vonno

Steven H. Voldman

Wesley H. Morris