Details
System-on-Chip Security
Validation and Verification|
85,59 € |
|
| Verlag: | Springer |
| Format: | |
| Veröffentl.: | 22.11.2019 |
| ISBN/EAN: | 9783030305963 |
| Sprache: | englisch |
Dieses eBook enthält ein Wasserzeichen.
Beschreibungen
<p>This book describes a wide variety of System-on-Chip (SoC) security threats and vulnerabilities, as well as their sources, in each stage of a design life cycle. The authors discuss a wide variety of state-of-the-art security verification and validation approaches such as formal methods and side-channel analysis, as well as simulation-based security and trust validation approaches. This book provides a comprehensive reference for system on chip designers and verification and validation engineers interested in verifying security and trust of heterogeneous SoCs.<br></p>
<p>Introduction.- Security Verification Using Formal Methods.- Simulation-Based Security Validation Approaches.- Security Validation Using Side-Channel Analysis.- Automated Vulnerability Detection And Mitigation.- Conclusion.</p>
<p><b>Farimah Farahmandi</b> is an assistant professor in the Department of Electrical and Computer Engineering at the University of Florida. She received her Ph.D. from the Department of Computer and Information Science and Engineering at the University of Florida, 2018. She received her B.S. and M.S. from the Department of Electrical and Computer Engineering at the University of Tehran, Iran in 2010 and 2013, respectively. Her research interests include design automation of System-on-Chips and energy-efficient systems, formal verification, hardware security validation, and post-silicon validation and debug. Her research has resulted in two books, seven book chapters, and several publications in premier ACM/IEEE journals and conferences including IEEE Transactions on Computers, IEEE Transactions on CAD, Design Automation Conference (DAC), and Design Automation and Test in Europe (DATE). Her research has been recognized by several awards including IEEE System Validation and Debug Technology Committee Student Research Award, Gartner Group Info-Tech Scholarship, a nomination for the Best Paper Award in ASPDAC 2017, and DAC Richard Newton Young Student Fellowship. She has actively collaborated with various research groups (IBM, Intel, and Cisco) that has led to several joint publications. She currently serves as an Associate Editor of IET Computers & Digital Techniques. She also has served on many technical program committees as well as organizing committees of premier ACM and IEEE conferences. Her research has been sponsored by AFRL, DARPA, and Cisco. She is a member of IEEE and ACM.</p>
<p><b>Yuanwen Huang </b>received his Ph.D. degree in Computer Engineering at University of Florida, in 2017. He received his B.E. (Hons.) degree at the Huazhong University of Science and Technology, China, in 2012. His research interests include energy-aware computing, hardware trust validation, system-on-chip verification, and storage and file systems. He has published more than 10papers in peer-reviewed conferences including CCS, DATE, ASPDAC, and ICCD, and transactions including IEEE TCAD, IEEE TIFS and ACM TECS. He received the Best Paper Award from the International Symposium on Quality Electronic Design in 2016. He received the DAC (Design Automation Conference) Richard Newton Young Fellowship award in 2016. He served in the Technical Program Committee for the international conference VLSI Design 2019. He is currently a software engineer at VMware, working on development in storage and file systems. </p>
<b>Prabhat Mishra</b> is a Professor in the Department of Computer and Information Science and Engineering at the University of Florida. His research interests include embedded and cyber-physical systems, hardware security and trust, network-on-chip architecture, energy-aware computing, formal verification, system-on-chip validation, and post-silicon debug. He received his Ph.D. in Computer Science and Engineering from the University of California atIrvine in 2004. His research has been recognized by several awards including the NSF CAREER Award, IBM Faculty Award, three Best Paper Awards, and EDAA Outstanding Dissertation Award. Prof. Mishra currently serves as an Associate Editor of ACM Transactions on Design Automation of Electronic Systems, IEEE Transactions on VLSI Systems, and Journal of Electronic Testing. He is an ACM Distinguished Scientist and a Senior Member of IEEE.
<p><b>Yuanwen Huang </b>received his Ph.D. degree in Computer Engineering at University of Florida, in 2017. He received his B.E. (Hons.) degree at the Huazhong University of Science and Technology, China, in 2012. His research interests include energy-aware computing, hardware trust validation, system-on-chip verification, and storage and file systems. He has published more than 10papers in peer-reviewed conferences including CCS, DATE, ASPDAC, and ICCD, and transactions including IEEE TCAD, IEEE TIFS and ACM TECS. He received the Best Paper Award from the International Symposium on Quality Electronic Design in 2016. He received the DAC (Design Automation Conference) Richard Newton Young Fellowship award in 2016. He served in the Technical Program Committee for the international conference VLSI Design 2019. He is currently a software engineer at VMware, working on development in storage and file systems. </p>
<b>Prabhat Mishra</b> is a Professor in the Department of Computer and Information Science and Engineering at the University of Florida. His research interests include embedded and cyber-physical systems, hardware security and trust, network-on-chip architecture, energy-aware computing, formal verification, system-on-chip validation, and post-silicon debug. He received his Ph.D. in Computer Science and Engineering from the University of California atIrvine in 2004. His research has been recognized by several awards including the NSF CAREER Award, IBM Faculty Award, three Best Paper Awards, and EDAA Outstanding Dissertation Award. Prof. Mishra currently serves as an Associate Editor of ACM Transactions on Design Automation of Electronic Systems, IEEE Transactions on VLSI Systems, and Journal of Electronic Testing. He is an ACM Distinguished Scientist and a Senior Member of IEEE.
This book describes a wide variety of System-on-Chip (SoC) security threats and vulnerabilities, as well as their sources, in each stage of a design life cycle. The authors discuss a wide variety of state-of-the-art security verification and validation approaches such as formal methods and side-channel analysis, as well as simulation-based security and trust validation approaches. This book provides a comprehensive reference for system on chip designers and verification and validation engineers interested in verifying security and trust of heterogeneous SoCs.<div><br></div><div><p></p><ul><li>Outlines a wide variety of hardware security threats and vulnerabilities as well as their sources in each of the stages of a design life cycle;</li><li>Summarizes unsafe current design practices that lead to security and trust vulnerabilities;</li><li>Covers state-of-the-art techniques as well as ongoing research efforts in developing scalable security validation using formal methods including symbolic algebra, model checkers, SAT solvers, and theorem provers;</li><li>Explains how to leverage security validation approaches to prevent side-channel attacks;</li><li>Presents automated debugging and patching techniques in the presence of security vulnerabilities;</li><li>Includes case studies for security validation of arithmetic circuits, controller designs, as well as processor-based SoCs.</li></ul><p></p><p></p><p></p></div>
Outlines a wide variety of hardware security threats and vulnerabilities as well as their sources in each of the stages of a design life cycle Summarizes unsafe current design practices that lead to security and trust vulnerabilities Covers state-of-the-art techniques as well as ongoing research efforts in developing scalable security validation using formal methods including symbolic algebra, model checkers, SAT solvers, and theorem provers Explains how to leverage security validation approaches to prevent side-channel attacks Presents automated debugging and patching techniques in the presence of security vulnerabilities Includes case studies for security validation of arithmetic circuits, controller designs, as well as processor-based SoCs
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